Conventional frequency synthesizers generally include a phase-locked loop (PLL). A PLL is a device that generates an output frequency that is a function of a reference frequency. When implemented in a device such as a wireless transceiver, the output frequency of the PLL may change frequently. For example, the output frequency of the PLL changes at start-up and when changing channels. In each of these situations, it is desirable for the PLL to settle as quickly as possible on a desired output frequency. Further, in frequency hopping spread spectrum (FHSS) transceivers, the output frequency of the PLL changes for each frequency hop. Thus, the PLL is required to have an even faster settling time in order to comply with the timing requirements of the frequency hopping transceiver. One PLL system starts with a coarse tuning mode for rapid frequency tuning before switching to a fine tuning mode for stabilization and final settling. A controllable oscillator in the PLL system may use a tunable element with discrete steps, such as a selectable capacitor bank, for coarse tuning, and may use a continuously tunable element, such as one or more varactor diodes, for fine tuning.
In conventional PLLs there is a trade-off between settling time and phase noise, which are both a function of the gain, and the pole and zero locations in the PLL, which is well known to those skilled in the art of PLL design. The use of coarse tuning systems further adds to the start-up or settle time of the oscillator. Thus, a designer may be forced to select a bandwidth for the loop that meets the phase noise requirements while providing a less than desirable settling time, and vice versa. Thus, there remains a need for a frequency synthesizer that avoids the trade-off between settling time and phase noise, and that has a reduced settling time.